x86-64-v5? The Future Of x86-64 Micro-Architecture Feature Levels
Questions arise about potential x86-64-v5 micro-architecture feature levels for future processors. Discussions on LLVM Discourse suggest incorporating latest AMD and Intel CPU ISA features, impacting upcoming Zen 4 and Icelake Server processors. Integration challenges with AVX10 256-bit remain unresolved.
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Questions have emerged regarding the potential development of x86-64-v5 micro-architecture feature levels for future processors. The existing x86-64 feature levels, such as x86-64-v2, v3, and v4, have been established to enhance CPU instruction set architecture (ISA) features beyond baseline specifications. The discussion around x86-64-v5 was initiated on the LLVM Discourse, suggesting a new target that could incorporate the latest AMD and Intel CPU ISA features, potentially benefiting upcoming AMD Zen 4 and Intel Icelake Server processors. However, no concrete steps have been taken towards implementing x86-64-v5 yet. Challenges have been raised internally, particularly concerning how to integrate AVX10 256-bit into x86-64-vN feature levels, given the uncertainty around widespread adoption of AVX-512. The outcome of these discussions will be crucial in determining the direction of future CPU ISA features and x86-64 feature level versions.
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