An SVE backend for astcenc (Adaptive Scalable Texture Compression Encoder)

The article discusses the implementation of a Scalable Vector Extension (SVE) backend for the astcenc compression tool, leveraging the new SIMD instruction set introduced in recent Arm CPUs. SVE allows for variable vector lengths, enabling CPUs to optimize performance without needing a new ISA for each design. The author highlights the advantages of SVE, including predicated operations that streamline data processing and native scatter/gather operations that enhance efficiency over previous NEON implementations. The implementation of a fixed-width 256-bit SVE version was chosen for astcenc due to compatibility with existing code and performance considerations. Initial performance results showed a significant uplift of 14 to 63%, particularly benefiting larger block sizes. The author notes that SVE reduces pressure on instruction decoders and register files, leading to fewer loop iterations and improved functionality. Future work may involve exploring SVE2 and developing a new codec using integer types to further optimize performance. The article concludes with a list of notable operations that have improved performance compared to NEON equivalents.

- The SVE backend for astcenc utilizes a fixed-width 256-bit implementation for optimization.

- Performance improvements ranged from 14% to 63%, especially for larger block sizes.

- SVE introduces advantages like predicated operations and native scatter/gather instructions.

- Future developments may include exploring SVE2 and creating a new codec with integer types.

- The implementation demonstrates significant efficiency gains over previous NEON-based methods.