April 1st, 2025

Measuring Acceleration Structures

The article analyzes memory consumption of Bounding Volume Hierarchies in ray tracing across various GPUs, revealing NVIDIA's lower usage compared to AMD, and emphasizes the impact of driver performance and standardization issues.

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Measuring Acceleration Structures

The article discusses the measurement of acceleration structures used in hardware-accelerated ray tracing, specifically focusing on the Bounding Volume Hierarchy (BVH) and its memory consumption across different GPUs. The author, Arseny Kapoulkine, highlights the lack of standardization in data layouts for acceleration structures among vendors, which complicates performance comparisons. An experimental setup using the Amazon Lumberyard Bistro scene is described, where various GPUs from AMD, NVIDIA, and Intel were tested to measure the size of the BVH. Results indicate significant disparities in memory consumption, with NVIDIA GPUs generally exhibiting lower memory usage compared to AMD counterparts. The article also emphasizes the role of drivers in influencing memory efficiency, noting improvements in AMD's driver performance over time. The author provides a theoretical framework for understanding BVH memory requirements, discussing the relationship between triangle nodes and box nodes, and the implications of using different data formats (fp16 vs. fp32). The analysis reveals that while memory consumption varies widely, the efficiency of the BVH structure is crucial for ray tracing performance.

- The article examines the memory consumption of acceleration structures in ray tracing across different GPU vendors.

- Significant differences in memory usage were found, with NVIDIA GPUs generally consuming less memory than AMD GPUs.

- Driver performance plays a critical role in the efficiency of memory consumption for acceleration structures.

- Theoretical models are proposed to understand the relationship between triangle and box nodes in BVH structures.

- The study highlights the lack of standardization in acceleration structure layouts among different hardware vendors.

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