Linus Torvalds says RISC-V will make the same mistakes as Arm and x86

Bad headline, he prefaces the statement with "I fear", `says` could've been written `fears`

It's realistic to expect RISC-V's execution won't be (& hasn't been) flawless

The context is re spectre

> RISC-V is an open-standard ISA for processors that is slowly gaining traction, especially in China, where some tech companies are using it to bypass America’s sanctions on the country.

I really don't like that narrative, it doesn't even make sense as MIPS already exists and is more than sufficient for the applications RISC-V is being used in. The same could be said about Linux but it's obvious how ridiculous it would be to bring that up.

One thing that I learned when becoming a senior engineer is that if the layer above you is profitable enough you should build substandard implementations in your layer that match the abstractions of the above layer. Overall the system will perform much better than if you optimize for whatever the bottleneck on your layer is.

Source video/interview:

https://news.ycombinator.com/item?id=40944164

Any offers on how long it will it be before were talking about Windows RISC-V machines?

I just upgraded my 6 year old Lenovo X1 and was pretty close to pulling the trigger on an ARM (Snapdragon) machine but felt too unproven and I knew there would be software issues for some of the things I needed to do so sticking with x86 (AMD).

I can easily see the decision next time going the other way or even RISC-V if the sofware is there to match.

Which mistakes is he referring to concretely?

Not exactly nostradamus to predict things wont go perfectly. But that's the thing about history, it gives you a chance not to make the same mistakes. Will RISCV have learnt history?

it sounds to me like complex instructions are unavoidable unless the use case is restricted to microcontrollers. A modern ISA should CPU feature flags that allow implementers to disable complex and expensive instruction sets.

Would it be fair to day that ARM for example is a CISC/RISC hybrid, where armv8-a is full on CISC but armv8-m is RISC proper? But that's what I'm suggesting anyways.

the "futuristic world if <X> was true" meme fully applies to the core idea that sw guys don't get the hw (and vice versa). even more true for the business people that leave no room for bridging the gap.

abstractions exist for a reason but it is refreshing to see some examples where researchers leverage the underlying hw architecture (see mamba architecture that works around GPU design - https://news.ycombinator.com/item?id=38932350). but we can do so much more instead of pushing the new version of the existing process node.

1. Want a simpler ISA

2. Build it

3. Realize adding a complex instruction that's weird can really boost performance in key use cases

4. Repeat 3 until someone thinks your ISA is overcomplicated and makes a new one

They had one job: make it similar to ARMv8-A but not too similar to give ARM any ideas. Look at SSE4/AVX2 and NEON and make sufficiently similar vector extensions to that as well.

So far RISC-V has failed miserably at both. "Just solve it in decoder", "just fuse common idioms", "just make vsetvli fast". Sure. Not like designers of ARMv8 or X86S had decades of prior experience to make better decisions.

Can someone please create an instruction set where the entire instruction set is implemented (even if in microcode) on every processor that uses that instruction set?

Have you looked at RISC-V or x64? They are messes of instruction set extensions, most of which reuse the same opcodes.

We have terabytes of disk space and gigabytes of RAM. We can afford a few extra bits in the opcode.