Intel vs. Samsung vs. TSMC
Competition intensifies among Intel, Samsung, and TSMC in the foundry industry. Focus on 3D transistors, AI/ML applications, and chiplet assemblies drives advancements in chip technology for high-performance, low-power solutions.
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The competition between Intel, Samsung, and TSMC in the foundry industry is intensifying as they each pursue their own paths towards advancements in chip technology. All three companies are focusing on 3D transistors and packages, with plans for transistor scaling down to the 18/16/14 angstrom range. The key drivers behind these advancements are AI/ML applications and the increasing data processing demands. The shift towards mass customization and heterogeneous chiplet assemblies is a significant development, requiring innovative connectivity schemes and engineering disciplines to work together effectively.
Intel, Samsung, and TSMC are all investing in various technologies such as EMIB, RDL bridges, and 3D-ICs to address the challenges of heat dissipation and complex chiplet integration. Each company has its own approach to connecting chiplets and enabling customization, with TSMC introducing a new language called 3Dblox for top-down design. The goal for these foundries is to offer more options for developing high-performance, low-power chips to meet the evolving needs of companies like Google, Meta, Microsoft, and Tesla. The future of chip design involves a mix of specialized and general-purpose processors at advanced process nodes to enhance performance and energy efficiency, particularly crucial for AI/ML applications.
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- Advanced packaging now requires similar precision and clean environments as chipmaking, with added complexity from microfluidics.
- Chip design and manufacturing are seen as highly complex and almost magical processes.
- There is interest in the development of chiplet/stacked die technology, with discussions on design and integration costs, and the challenges of multi-die design.
- TSMC's description language is noted as an "open" standard, with references to resources for further information.
- Speculation on the future of node shrinks and the potential for more granular marketing steps in semiconductor advancements.
11 commentshttps://semiwiki.com/eda/synopsys/347420-the-immensity-of-so...
TSMC also discussed some of the challenges for multi-die design a month ago:
https://semiwiki.com/semiconductor-manufacturers/tsmc/345909...
My take is that the rapid rise in heterogeneous solutions and complexity will provide some excess semi profitability, but at the cost of long run performance increases for "new nodes". Instead of one path forward there are now many.
Or the most recent:
https://semiwiki.com/semiconductor-manufacturers/347646-tsmc...
https://resources.sw.siemens.com/en-US/video-simplified-phys...
If the article is correct that the major semis are going to kind of forge their own paths, in my opinion, that means marketing lots of even 1/3 or quarter steps.
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