An Interview with Intel's Arik Gihon about Lunar Lake at Hot Chips 2024

Intel's Arik Gihon discussed the Lunar Lake architecture during an interview at Hot Chips 2024. Gihon, an SoC architect at Intel, has been involved in the project for three years, leading the architecture team from its initial definition to high-volume manufacturing. He explained that the decision to exclude Simultaneous Multithreading (SMT) was based on a shift towards more efficient multi-threading through E-cores, which allows for better single-thread performance without increasing power consumption. The architecture has also moved E-cores off the ring to a low-power island to enhance efficiency. Gihon highlighted improvements in latency due to a new intermediate L1 cache and discussed the benefits of a monolithic design for the GPU and SoC components, which allows for better performance and reduced latency. The integration of PCIe 5 was justified by the need for higher bandwidth to support Gen 5 SSDs, despite concerns about power efficiency. Gihon concluded the interview by sharing his favorite cheese, Kashkaval.

- Arik Gihon leads the SoC architecture team for Intel's Lunar Lake project.

- SMT was removed to enhance single-thread performance and efficiency through E-cores.

- E-cores have been relocated to a low-power island for improved efficiency.

- The new L1 cache structure is designed to reduce latency.

- PCIe 5 was adopted to support higher bandwidth for Gen 5 SSDs.