Hynix launches 321-layer NAND
Hynix has begun mass production of the first 321-layer NAND with 1Tb capacity, featuring improved write and read times, enhanced productivity, and plans for customer delivery in early 2025.
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Hynix has commenced mass production of the world's first 321-layer NAND, a triple-level cell-based 4D memory with a capacity of 1Tb. This follows the company's previous launch of a 238-layer NAND in June 2023, marking Hynix as the first supplier to exceed 300 layers in tNAND technology. The new 321-layer device boasts a 12% improvement in write time and a 13% enhancement in read time compared to its predecessor. Hynix achieved this technological advancement by implementing a "3 plugs" process technology, which optimally connects three plugs after completing three plug processes. Additionally, the company developed a low-stress material and introduced technology for automatic alignment correction among the plugs. By utilizing the same development platform as the 238-layer NAND, Hynix improved productivity by 59% compared to the previous generation, minimizing disruptions from process changes. The company plans to deliver the 321-layer products to customers in the first half of 2025.
- Hynix has launched the first 321-layer NAND with 1Tb capacity.
- The new NAND offers significant improvements in write and read times.
- The "3 plugs" process technology enabled the stacking of over 300 layers.
- Productivity increased by 59% compared to the previous generation.
- Products will be available to customers in the first half of 2025.
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- Several users discuss the implications of the 321-layer design, questioning the manufacturing process and the number of layers needed for each cell.
- There is interest in the potential for increased storage capacity and reduced costs for future SSDs.
- Some commenters reflect on the advancements in NAND technology over the years, expressing amazement at the engineering feats achieved.
- Questions arise about the yield and reliability of the new memory, with concerns about bad bits during testing.
- A few users express a desire for improvements in other memory types, such as smaller SPI flash for embedded applications.
11 commentshttps://thememoryguy.com/3d-nands-impact-on-the-equipment-ma...
This (the past 20 years of improvement) is an incredible feat of engineering.
How many layers are needed for each physical cell? Is it 1,2, or a lot more? Is this effectively 321 physical TLC cells stacked vertically and some planar style logic at the bottom of the stack.
Also, where do multiple pieces of silicon factor into this - I assume we might be up to 16 silicon dies deep with through-silicon-vias, which would mean a cross section of a package could actually have 5000 layers - that sounds crazy!
This would hopefully bring down the price of 4TB and 8TB SSD in the near future.
What does 4D memory mean?
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