JEDEC Plans LPDDR6-Based CAMM, DDR5 MRDIMM Specifications
JEDEC is developing DDR5 MRDIMM standards for servers, aiming to double peak bandwidth and support more than two ranks. Micron introduced the first DDR5 MRDIMMs for Intel's Xeon 6 servers. LPDDR6 CAMMs will feature wider memory buses and new connector arrays.
Read original article
JEDEC is developing standards for DDR5 Multiplexed Rank DIMMs (MRDIMM) for servers and an updated LPCAMM standard for next-generation LPDDR6 memory. Micron recently introduced the industry's first DDR5 MRDIMMs, set to launch with Intel's Xeon 6 server platforms. MRDIMMs use DDR5 components but introduce multiplexing for improved performance and increased memory module capacity. The standard aims to double peak bandwidth to 12.8 Gbps and support more than two ranks. Additionally, a "Tall MRDIMM" form factor is in development to enable higher capacity DIMMs using commodity DRAM chips. On the other hand, LPDDR6 CAMMs will feature wider memory buses and new connector arrays to accommodate the memory type's advancements. JEDEC is targeting a 24-bit subchannel/48-bit channel design for LPDDR6 CAMMs. While MRDIMMs are already shipping for Intel systems, the completion timeline for both memory module standards is not specified.
Related
Leaked Arrow Lake diagram show more PCIe lanes, no DDR4, 2 M.2 SSD ports to CPU
The leaked Intel Arrow Lake chipset details upgrades like PCIe lanes increase, DDR5 support, dual M.2 SSD ports, Thunderbolt 4 integration, Arc Xe-LPG graphics, USB 3.2 Gen connections, and networking options. Insights into upcoming advancements.
GPUs can now use PCIe-attached memory or SSDs to boost VRAM capacity
Major companies like AMD, Intel, and Nvidia are considering supporting Panmnesia's CXL IP for GPU memory expansion using PCIe-attached memory or SSDs. Panmnesia's low-latency solution outperforms traditional methods, showing promise for AI/HPC applications. Adoption by key players remains uncertain.
GPUs can now use PCIe-attached memory or SSDs to boost VRAM capacity
Major companies like AMD, Intel, and Nvidia are considering supporting Panmnesia's CXL IP technology for GPU memory expansion using PCIe-attached memory or SSDs. The low-latency CXL IP addresses increasing memory needs for AI training datasets, offering improved GPU performance for AI and HPC applications. Adoption by GPU manufacturers is uncertain, potentially shaping future GPU memory expansion technologies.
Linux Looking to Make 5-Level Paging Support Unconditional for x86_64 Builds
Intel introduces 5-level paging in Linux kernel for expanded memory sizes. Default in Linux 5.5 for Intel Ice Lake and AMD Zen 4 CPUs. Simplifies kernel configuration for modern hardware demands.
An interview with AMD's Mike Clark, 'Zen Daddy' says 3nm Zen 5 is coming fast
AMD's Mike Clark discusses Zen 5 architecture, covering 4nm and 3nm nodes. 4nm chips launch soon, with 3nm to follow. Zen 'c' cores may integrate into desktop processors. Zen 5 enhances Ryzen CPUs with full AVX-512 acceleration, emphasizing design balance for optimal performance.
1 commentsRelated
Leaked Arrow Lake diagram show more PCIe lanes, no DDR4, 2 M.2 SSD ports to CPU
The leaked Intel Arrow Lake chipset details upgrades like PCIe lanes increase, DDR5 support, dual M.2 SSD ports, Thunderbolt 4 integration, Arc Xe-LPG graphics, USB 3.2 Gen connections, and networking options. Insights into upcoming advancements.
GPUs can now use PCIe-attached memory or SSDs to boost VRAM capacity
Major companies like AMD, Intel, and Nvidia are considering supporting Panmnesia's CXL IP for GPU memory expansion using PCIe-attached memory or SSDs. Panmnesia's low-latency solution outperforms traditional methods, showing promise for AI/HPC applications. Adoption by key players remains uncertain.
GPUs can now use PCIe-attached memory or SSDs to boost VRAM capacity
Major companies like AMD, Intel, and Nvidia are considering supporting Panmnesia's CXL IP technology for GPU memory expansion using PCIe-attached memory or SSDs. The low-latency CXL IP addresses increasing memory needs for AI training datasets, offering improved GPU performance for AI and HPC applications. Adoption by GPU manufacturers is uncertain, potentially shaping future GPU memory expansion technologies.
Linux Looking to Make 5-Level Paging Support Unconditional for x86_64 Builds
Intel introduces 5-level paging in Linux kernel for expanded memory sizes. Default in Linux 5.5 for Intel Ice Lake and AMD Zen 4 CPUs. Simplifies kernel configuration for modern hardware demands.
An interview with AMD's Mike Clark, 'Zen Daddy' says 3nm Zen 5 is coming fast
AMD's Mike Clark discusses Zen 5 architecture, covering 4nm and 3nm nodes. 4nm chips launch soon, with 3nm to follow. Zen 'c' cores may integrate into desktop processors. Zen 5 enhances Ryzen CPUs with full AVX-512 acceleration, emphasizing design balance for optimal performance.