Engineers develop new two-dimensional, low-power- field-effect transistor
Engineers from Shanghai Institute and collaborators developed a low-power two-dimensional field-effect transistor to reduce smartphone recharges, addressing gate leakage and dielectric strength issues, crucial for 5G and IoT applications.
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A team of engineers from the Shanghai Institute of Microsystem and Information Technology, in collaboration with researchers from City University of Hong Kong and Fudan University, has developed a new two-dimensional field-effect transistor (FET) that operates with low power consumption. This innovation aims to reduce the frequency of smartphone recharges. The research, published in the journal Nature, addresses challenges such as high gate leakage and low dielectric strength that have hindered the miniaturization of silicon-based transistors. The team utilized single-crystalline aluminum oxide, only 1.25 nm thick, to create FETs with an aluminum gate measuring 100 µm wide and 250 nm long, ensuring complete insulation by leaving a gap between the gates. The fabrication process involved standard van der Waals transfer methods to align the materials on a wafer. This advancement is significant for the development of smaller, more efficient devices, particularly in the context of 5G technology and Internet of Things (IoT) applications, where reducing device size is crucial. The researchers believe that the use of 2D materials could mitigate issues related to short-channel effects that current materials face.
- Engineers have developed a low-power, two-dimensional field-effect transistor.
- The innovation could lead to less frequent smartphone recharging.
- The research addresses high gate leakage and low dielectric strength issues.
- Single-crystalline aluminum oxide was used to enhance performance.
- This advancement is important for 5G and IoT device miniaturization.
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