Ubitium is developing 'universal' processor combining CPU, GPU, DSP, and FPGA
Ubitium is developing a Universal Processor integrating CPU, GPU, DSP, and FPGA functionalities, targeting a 2026 launch. The startup raised $3.7 million, raising concerns about feasibility and timeline.
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Ubitium, a RISC-V startup, has announced the development of a "Universal Processor" that integrates CPU, GPU, DSP, and FPGA functionalities into a single architecture. This processor aims to be a paradigm shift in the semiconductor industry, designed to be workload-agnostic and capable of reusing all transistors for various tasks without the need for specialized cores. Ubitium's CEO, Hyun Shin Cho, emphasizes that this chip is essential for the AI era. The company has raised $3.7 million to fund the development of prototypes and kits, although this amount is considered insufficient for a project of this scale, which typically requires hundreds of millions for production. The Universal Processor is expected to launch in 2026, but experts suggest this timeline may be overly ambitious given the complexities involved in chip development. Ubitium plans to create a range of chips based on the same microarchitecture, targeting applications from embedded devices to high-performance computing systems. The team behind Ubitium consists of semiconductor veterans from major companies, but the startup's financial backing and ambitious timeline raise questions about its feasibility.
- Ubitium is developing a Universal Processor that combines multiple processing functionalities.
- The chip is based on RISC-V architecture and aims to be more energy-efficient and cost-effective.
- The company has raised $3.7 million, which may not be enough for full development.
- A 2026 launch date is considered ambitious due to the complexities of chip development.
- Ubitium plans to offer a portfolio of chips for various applications, from embedded devices to high-performance systems.
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7 commentshttps://milkv.io/duo-s This has a RISC/V, Cortex, a TPU and of course the much beloved 8051.
Our runtime reconfigurability comes from adaptive [5] load-balancing [1] JIT compilers (at runtime) that reconfigure hardware or generate hardware blocks at runtime with Morphle Logic [4].
We have 8-bit slices that you can combine per [block of] instructions into teams to make CPU or GPU or DSP or TPU cores and fine grained logic cells to make FPGA fabric and interconnect networks.
Like Transmeta and Apple Silicon our processors also are optimized to emulate bytecode, Intel, ARM and RISC-V instructions. With large teams of 80 8-bit slices we can emulate Intel instruction blocks several times faster than high-end Xeon or AMD ZEN 4 cores can run them.
[1] https://vimeo.com/731037615
[2] https://scholar.google.com/citations?user=mWS92YsAAAAJ&hl=en...
[3] https://scholar.google.com/citations?user=6wa49gkAAAAJ&hl=en
[4] https://github.com/fiberhood/MorphleLogic/blob/main/README_M...
One has doubts, especially with only $3.7 million in funding so far.
I recall that Sun's MAJC processor had functional/instruction units that were generic - there weren't dedicated floating point or integer or simd units, they could all operate on any instruction.
It's hard to tell whether their thing is yet another take on the sea-of-cores model, or something more interesting. They talk in terms of risc-v, so maybe it's a lot of cores, with something new. Their website seems to point at compilers being important - I guess as that means that their goal is to leverage risc-v but extend it to give the compiler more ways to express data and compute location.
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