August 24th, 2024

UCIe 2.0 for 3D Chip Structures Offers up to 75 Times More Bandwidth

UCIe 2.0 enhances chip design with 75 times more bandwidth than UCIe 1.1, supporting 3D structures, 4 GT/s transfer speeds, and collaboration among major manufacturers, aiming for 2028 advancements.

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UCIe 2.0 for 3D Chip Structures Offers up to 75 Times More Bandwidth

The Universal Chiplet Interconnect 2.0 (UCIe 2.0) is set to revolutionize chip design by offering up to 75 times more bandwidth than its predecessor, UCIe 1.1. This new interconnect specification is tailored for advanced 3D chip structures, where chiplets are stacked vertically, enhancing speed and power efficiency. The UCIe 2.0 protocol allows for more communication channels between chiplets, significantly improving bandwidth density and reducing power consumption. It supports a transfer speed of up to 4 GT/s per channel, with the potential for bandwidth density to reach 300 terabytes per second per square millimeter at a bump pitch of one micron. The UCIe 2.0 also introduces tools for managing and testing chiplets, improving their manufacturability and reliability. Major industry players, including Nvidia, Intel, and TSMC, are part of the UCIe consortium, which aims to standardize this technology. While there is no definitive timeline for market-ready chips based on UCIe 2.0, the consortium is committed to releasing new specifications annually. The shift to 3D designs is expected to surpass traditional monolithic die structures by 2028, marking a significant evolution in semiconductor technology.

- UCIe 2.0 offers up to 75 times more bandwidth than UCIe 1.1.

- The new specification supports advanced 3D chip structures with improved power efficiency.

- It allows for a transfer speed of up to 4 GT/s per channel.

- Major chip manufacturers are collaborating within the UCIe consortium.

- The transition to 3D designs is projected to outpace traditional chip designs by 2028.

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By @peter_d_sherman - 3 months
>"Each chiplet has its own communications component – a NOC (network on chip) – that speeds up communication between chiplets.

“We start at 4000 gigabytes per second per square millimeter, and we go all the way up to 300,000 gigabytes per second — or 300 terabytes per second — per square millimeter once we hit one micron, a huge amount of bandwidth,” said Das Sharma."