ARM or x86? ISA Doesn't Matter (2021)
The debate between ARM and x86 ISAs reveals that performance differences are diminishing, with microarchitectural design being more influential than ISA. Both architectures employ similar efficiency techniques, emphasizing implementation choices.
Read original articleThe ongoing debate between ARM and x86 instruction set architectures (ISAs) has been a focal point in discussions about CPU performance. However, recent insights suggest that the differences in ISAs are less significant than previously thought. Notably, Jim Keller, a prominent CPU designer, argues that the historical distinctions between CISC (x86) and RISC (ARM) have largely converged, with modern performance being dictated more by microarchitectural design than by the ISA itself. Research indicates that both ARM and x86 CPUs have been optimized for different use cases, leading to variations in power consumption and performance, but not due to inherent advantages of one ISA over the other. Studies have shown that the complexity of decoding instructions, often cited as a disadvantage for x86, does not significantly impact performance in high-end CPUs. Both architectures have adopted similar techniques, such as micro-op caches, to mitigate decoding costs. Furthermore, ARM instructions can also decode into multiple micro-operations, challenging the notion of ARM's efficiency. Ultimately, the conclusion is that the implementation of the CPU design is far more critical than the ISA, and competition in the high-performance CPU market is driven by design choices rather than instruction set differences.
- The differences between ARM and x86 ISAs are becoming less relevant in terms of performance.
- Modern CPU performance is more influenced by microarchitectural design than by the ISA itself.
- Both ARM and x86 have adopted similar techniques to improve efficiency, such as micro-op caches.
- ARM instructions can decode into multiple micro-operations, challenging the efficiency narrative.
- Implementation choices are more critical than ISA differences in the high-performance CPU market.
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[1] https://www.tomshardware.com/news/tenstorrent-shares-roadmap...
[2] https://www.anandtech.com/show/21281/tenstorrent-licenses-ri...
I wonder which ones he considers those to be -- the interview doesn't say, sadly...
This [variable-length coding] is a disadvantage for x86, yet it doesn’t really matter for high performance CPUs ...
Why are they leaving out difficilty of building a compiler backend when the ISA has variable-length codes? I would assume an ISA needs to consider its burden on compiler authors. (Itanium is an extreme example of an ISA too tedious for compiler authors)I once extended a Common Lisp compiler to emit machine code for SSE4.2 instructions (specifically minss and maxss). The experience was a bit bad due to subtle differences in prefixes and specific fields needing to be set to activate some mode for SSE4.2 instructions.
Now suppose you want to debug a compiler backend targetting x86. Good luck, x86 disassembly is an undeciable problem because you don't know where the instructions start. Meanwhile ARM has two kinds of instructions (full-size and half-size, called "thumb"). Thanks to fixed-length instructions and alignment rules, you always know whether you're in thumb or not. Emitting machine code (and disassembly) is much more straightforward
Very amateur-ish question and counterpoint from me: how is Apple M1 performance and power consumption so good compared to the other laptop cpus then?
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