August 27th, 2024

ARM or x86? ISA Doesn't Matter (2021)

The debate between ARM and x86 ISAs reveals that performance differences are diminishing, with microarchitectural design being more influential than ISA. Both architectures employ similar efficiency techniques, emphasizing implementation choices.

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ARM or x86? ISA Doesn't Matter (2021)

The ongoing debate between ARM and x86 instruction set architectures (ISAs) has been a focal point in discussions about CPU performance. However, recent insights suggest that the differences in ISAs are less significant than previously thought. Notably, Jim Keller, a prominent CPU designer, argues that the historical distinctions between CISC (x86) and RISC (ARM) have largely converged, with modern performance being dictated more by microarchitectural design than by the ISA itself. Research indicates that both ARM and x86 CPUs have been optimized for different use cases, leading to variations in power consumption and performance, but not due to inherent advantages of one ISA over the other. Studies have shown that the complexity of decoding instructions, often cited as a disadvantage for x86, does not significantly impact performance in high-end CPUs. Both architectures have adopted similar techniques, such as micro-op caches, to mitigate decoding costs. Furthermore, ARM instructions can also decode into multiple micro-operations, challenging the notion of ARM's efficiency. Ultimately, the conclusion is that the implementation of the CPU design is far more critical than the ISA, and competition in the high-performance CPU market is driven by design choices rather than instruction set differences.

- The differences between ARM and x86 ISAs are becoming less relevant in terms of performance.

- Modern CPU performance is more influenced by microarchitectural design than by the ISA itself.

- Both ARM and x86 have adopted similar techniques to improve efficiency, such as micro-op caches.

- ARM instructions can decode into multiple micro-operations, challenging the efficiency narrative.

- Implementation choices are more critical than ISA differences in the high-performance CPU market.

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Link Icon 14 comments
By @janice1999 - 5 months
Since Jim Keller is quoted in the article, it would be good to point out that his new company uses RISC-V cores a lot [1] and have licensed their design out [2] to other companies. It seems to have been the correct choice for them.

[1] https://www.tomshardware.com/news/tenstorrent-shares-roadmap...

[2] https://www.anandtech.com/show/21281/tenstorrent-licenses-ri...

By @Mathnerd314 - 5 months
Say that when I need to run some program and I have an ARM processor but the only binaries available are x86...
By @remexre - 5 months
> it has got the right top eight instructions that you actually need to optimize for

I wonder which ones he considers those to be -- the interview doesn't say, sadly...

By @slashdave - 5 months
Isn't it kind of obvious that the instruction set itself cannot directly impact performance, since operations are just single clock cycles? I assume the issue is more about the difficulties of implementation, in particular how x86 has a lot of complicated archaic features and corner cases that just absorbs space on silicon, not to mention engineering effort. Apple, being vertically integrated, is free to toss features at will.
By @snvzz - 5 months
If ISA really does not matter, then RISC-V is a no-brainer, due to its licensing.
By @CalChris - 5 months
If ISAs really didn't matter then Apple would have switched horses.
By @jovial_cavalier - 5 months
So... why doesn't Intel "just" make a low-power x86 processor and win everything forever?
By @ksec - 5 months
Missing [2021] in the title.
By @koito17 - 5 months
This paragraph caught my attention

  This [variable-length coding] is a disadvantage for x86, yet it doesn’t really matter for high performance CPUs ...
Why are they leaving out difficilty of building a compiler backend when the ISA has variable-length codes? I would assume an ISA needs to consider its burden on compiler authors. (Itanium is an extreme example of an ISA too tedious for compiler authors)

I once extended a Common Lisp compiler to emit machine code for SSE4.2 instructions (specifically minss and maxss). The experience was a bit bad due to subtle differences in prefixes and specific fields needing to be set to activate some mode for SSE4.2 instructions.

Now suppose you want to debug a compiler backend targetting x86. Good luck, x86 disassembly is an undeciable problem because you don't know where the instructions start. Meanwhile ARM has two kinds of instructions (full-size and half-size, called "thumb"). Thanks to fixed-length instructions and alignment rules, you always know whether you're in thumb or not. Emitting machine code (and disassembly) is much more straightforward

By @bfung - 5 months
> Here in this article we’ll bring together research, comments from people who are very familiar with CPUs, and a bit of our in-house data to show why focusing on the ISA is a waste of time

Very amateur-ish question and counterpoint from me: how is Apple M1 performance and power consumption so good compared to the other laptop cpus then?